» Integrated USB transceiver

» Supports 24 MHz oscillator circuit with internal 48 MHz clock generation circuit

» Programmable clock generator, Serial Interface Engine (SIE) consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification 1.0 and 1.1 compliant

» Control/Status registers

» USB Function Controller with seven FIFO-based Endpoints:
    » One bi-directional Control Endpoint 0 (8 bytes)
    » Three Transmit Endpoints (64 bytes each)
    » Three Receive Endpoints (64 bytes each)

» 8-bit parallel interface with two selectable modes:
    » Non-multiplexed
    » Multiplexed (Intel compatible)

» Enhanced DMA support
    » Automatic DMA (ADMA) mode for fully CPU-independent transfer of large bulk or ISO packets
    » DMA controller, together with the ADMA logic, can transfer a large block of data in 64-byte packets via the USB
    » Automatic Data PID toggling/checking and NAK packet recovery (maximum 256x64 bytes of data = 16K bytes)

» MICROWIRE/PLUS interface